The present invention relates to DRAM cells, and more particularly, to techniques for storing data in and accessing data from DRAM cells.
Arrays of dynamic random access memory (DRAM) cells have been provided as an alternative to static random access memory (SRAM) storage technology. DRAMs require far less transistors than SRAM devices to store a given quantity of data bytes.
A DRAM cell can be fabricated using standard CMOS technology or other well known types of processing technology. One type of DRAM cell includes a small storage capacitor coupled to a single access transistor. This DRAM cell is a much smaller cell than a typical SRAM cell.
DRAM cells dynamically store data on storage capacitors. Because charge leaks from the capacitors, the cells must be refreshed periodically. A typical DRAM refresh cycle includes the steps of addressing the cells, sensing their contents (i.e. logic high or logic low), and writing the information back in the cells. To refresh DRAM cells, sense circuitry performs a read operation before writing data back. The sense circuitry typically includes sense amplifiers.
When data is read from a single-transistor DRAM cell, charge is drawn directly from the storage capacitor. For example, a stored high voltage will be pulled below the high supply voltage. Because a read operation disturbs the amount of charge stored on the cell capacitor, the operation of the memory array must be synchronized to avoid reading data in the cells during a refresh cycle. This requires more circuitry and tends to limit the operating speed of the circuit.
DRAM technology has been used in many integrated circuit applications. For example, a DRAM cell can be used as the programmable element in a programmable logic device (PLD) instead of an SRAM cell.
PLDs typically require that memory cells store charge at the full value of the supply voltage. The operation of a PLD is adversely effected when charge stored in memory is degraded during read cycles.
It would therefore be desirable to provide DRAM cells that output the full value of the supply voltage. It would also be desirable to provide DRAM cells that do not drain charge away from the storage node during read cycles so that the stored charge can be maintained at the supply voltage.